1. Field of Invention
The invention relates to a decoder and the decoding method thereof. In particular, the invention relates to a programmable Low-Density Parity-Check (LDPC) decoder that combines a programmable switch and a memory unit and the method thereof.
2. Related Art
Due to the improvements in semiconductor manufacturing processes and rapid developments in communication systems in recent years, not only are the communication systems using LDPC encoding realized, they always receive wide attentions because of their superior decoding efficiency and their ability in achieving the Shannon limit. The Shannon limit is the theoretical minimal bit error rate in a communication channel under a specific signal-to-noise ratio (SNR).
Generally speaking, a single-mode LDPC code decoder is to only decode a single fixed decoding matrix. However, such a decoder is not suitable for different communication environments. It is therefore not appropriate for future channel-adaptive communication systems.
In view of the foregoing, some vendors provide several decoding matrices in the decoder (the so-called multiple modes), so that the user can select an appropriate decoding matrix for different communication qualities. When interference in the communication channel becomes strong, one has to use a decoder with a larger decoding matrix. However, this method still cannot allow the user to arbitrarily adjust the size of the decoding matrix. Therefore, it still cannot be used in channel-adaptive communication systems.
In summary, the prior art has the problem that the decoders are not channel-adaptive. It is therefore desirable to provide a better technique.